Research on ESD and TVS Protection Technology in Semiconductor IC Package Test

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Abstract

With the development of the semiconductor process to 5 nm and below, ESD protection faces challenges. The TVS reduces the response time to 0.5 ns through the three-dimensional TSV structure, and the SiC / GaN material achieves high temperature protection of 200℃ and 15 kV. The multi-stage cooperative protection network combined with inverted welding and flexible substrate technology meets the IEC 61000-4-2:2024 and AEC-Q100-012 standards. The parasitic inductance was suppressed to < 0.05 nH in high-frequency scenarios, and the eWLB package verified the technical feasibility. Two-dimensional materials and intelligent monitoring system promote the evolution of ESD protection to the system level.

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